1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit devices implemented using a plurality of partially defective integrated circuit chips.
2. Related Art
There are many considerations which must be born in mind when designing a computer architecture for Very Large Scale Integrated (VLSI) chips. Several major considerations are discussed by Stephen B. Furber, in his text titled, VLSI RISC Architecture and Organization, (Marcel Dekker, Inc., 1989).
The cost of processing a particular size of wafer is roughly constant, but defects cause die costs to increase more rapidly than linearly with area. Chips above a certain area are effectively unmanufacturable. Therefore the functionality which is to go on a single chip must be specified very carefully to ensure that the economics of the product are appropriate. The designer must also be aware of the strongly two-dimensional nature of VLSI design, which makes the topology of the functions and connections between them extremely important.
Topologically efficient layouts (such as most memory devices) can contain an order of magnitude more transistors per unit area than interconnect dominated random logic structures. Estimating the eventual size of a layout from a logic diagram is hard.
An important aspect of VLSI is that the effort required to produce a design does not depend on the total number of transistors used so much as the number of different elementary (leaf or standard) cells required. Once a single register bit has been designed, it is relatively easy to replicate it to produce a register bank of arbitrary size. It is certainly quicker than generating a random logic function which uses far fewer transistors.
Therefore VLSI designers strive to build regular structures, which are based on tessellated arrays of standard cells. Currently, there are four groupings of regular structure approaches to ASIC design: sea-of-gates, gate arrays, standard cells and megacells (megacells being the most organized).
The intermediate approach to random logic is to use a cell library, where a set of standard gates, latches, flip-flops, etc. is designed and characterized, and the circuit designer picks up appropriate cells and wires them together. This approach does not yield the smallest possible layout, but the turn around time can be fast. It may also be a good way to implement a small amount of logic, which for one reason or another cannot be incorporated into a regular structure.
This design methodology can also be applied to Ultra Large Scale Integration (ULSI) chips as well. The difference being that in ULSI, the regular structures are larger and have more functionality. In ULSI the regular structures having unique functional features are called megacells.
It is hard to determine what is wrong with a VLSI device, not to mention a larger ULSI device, if it does not work, and trying to fix the problem once it is identified can take several months or more. There is therefore a great incentive to produce working devices based on an initial design. When the device has the complexity of a superscalar RISC processor, for example, this is not easy.
Once the design is correct, it is tempting to assume that mass production is straightforward. This assumption is false! When a large integrated circuit is manufactured in volume, at least half of the manufactured devices will not work. The defects which cause failure are varied and random, and all devices must be thoroughly tested to identify the rejects. The test program should exercise all the transistors on the chip to ensure they are functioning, and make sure that any failure will affect the measured outputs at the pins. Speed of critical paths must be measured to make sure that the transistors are up to the required performance, and so on.
1. Conventional Software Emulation
Several software simulation applications are commercially available for the testing of microelectronic devices such as microprocessors, and the like. Emulation on a behavior level and circuit analysis at the transistor level are two extreme possibilities. (A logic level simulator, such as SILOS, and a switching level simulator, such as Timemill, are intermediate simulation tools.)
A behavior level software simulation tool called Verilog, which is manufactured by Cadence Design Systems, Inc., San Jose, Calif., is conventionally used by many design houses to verify high level design concepts. Because the software simulation only takes into consideration behavioral operation, timing, layout and physics of the microelectronic device design are not accurately evaluated. For VLSI and ULSI microelectronic devices, this type of simulation is fine from an initial architecture point of view, but is a far cry from predicting whether the microelectronic device itself will work due to modeling limitation on circuit timing and loading. For instance, a bilateral circuit that propagates data to both directions, can have too strong a feedback circuit which may change the input if the transistor has a feedback loop exposed to the output node (when coupled with time, the result cannot be easily determined by Verilog).
Software applications which operate on the circuit analysis level are provide more accurate device emulation, but can take up to a few days to process one test vector on a microelectronic device including only 100 thousand transistors. Thus the processing of a meaningful number of test vectors is virtually impossible using for such circuit analysis software tools. An example of such a software simulator is SAGE, which is manufactured by Meta-Software, Inc., Campbell, Calif. A SAGE-type simulator is faster than a SPICE simulator, but even SAGE simulation is based on device models and approximated device equations, not to mention simulation resolution limitations, such as temperature and 3-D effects on devices and interconnections.
2. Conventional Field Programmable Gate Array Emulation
Quickturn Systems, Inc., of Mountain View, Calif., manufactures a 1 Mhz hardware emulator using field programmable gate arrays (FPGA), which is a about 10.sup.6 improvement over the software testing techniques discussed in the preceding section. Using this approach involves the programming of field programmable gate arrays, such as fused link PALs, EPROMs, EEPROMs, and the like, to logically construct building blocks to functionality match the proposed design for the microelectronic device to be tested. However, each logic design change for the microelectronic device being tested requires reprogramming and partitioning of the field programmable gate array. This hardware replacement or reprogramming is done at moderate cost and can be labor intensive, and takes time to verify the function.
Both conventional testing techniques, software and hardware, have a modeling accuracy problem, since the transistors and critical timing paths, as well as loading and coupling, not to mention more subtle device leakage and charge redistribution effects, are not actually tested.
Software applications, such as Verilog operating on a behavior model level take seconds or tenths of seconds to perform one test vector on a ULSI chip. But testing on the behavior model level does not provide the necessary modeling of each transistor and critical path as emphasized above.
The design and development of the test program absorbs as much effort as the logic design of the device itself, and can be greatly eased by careful consideration of test issues during the logic design phase. Considerable quantities of logic may be added just to simplify testing. Testing costs can be a significant proportion of the total device costs. Designing for testability is vital.
To translate a design into device/circuit models, Quickturn or other vendors would need to go through certain translation tables, and the result can put 5 to 10 times more devices on the FPGA type chip than the real circuit. The overhead can be tremendous. Imagine the size of a 4M transistor ULSI chip emulator at 40M transistors! Moreover, the amount or time required to burn-in or program that size FPGA emulator is considerable. It may take a team of engineers more than a year to generate the design translation to a testable stage.
These considerations affect architectural decisions in complex ways, and furthermore they are tied to semiconductor technology which is advancing rapidly. The constraints represent moving targets, a VLSI or ULSI architecture which is in some sense optimal at one point in time will cease to be so a few years later, and would have been unmanufacturable a few years earlier.
It is necessary, therefore, when designing an architecture for VLSI or ULSI, to estimate the time to complete the design and to implement it, and to match the design to the semiconductor technology which might reasonably be expected to be available at that future time.